Level shifters are used in current systems to level shift from a core power supply voltage to another power supply voltage. Conventional level shifters include a latch formed by two-cross-coupled inverters. For example, conventional level-shifter 100 shown in FIG. 1 includes a first inverter 115 formed by a serial stack of a PMOS transistor P1 and an NMOS transistor M2 that is cross-coupled with a second inverter 120 formed by another serial stack of a PMOS transistor P2 and an NMOS transistor M3. The drains of transistors P2 and M3 form a true output node (OUT) for level-shifter 100. Similarly, the drains of transistors P1 and M2 form a complement output node (OUTB). Cross-coupled inverters 115 and 120 are located within an input output (I/O) power domain powered by an I/O power supply voltage (VDDIO) that is greater than a core power supply voltage (VDD) that powers a pair of input inverters 105 and 110.
Inverter 105 inverts a true input signal IN into a complement input signal (INB) that drives a gate of a pull-down NMOS transistor M4 coupled between the output node and ground. Inverter 110 inverts the complement input signal back into the true input signal IN to drive a gate of a pull-down NMOS transistor M1 coupled between the complement output node OUTB and ground. Depending upon the state of the true input signal IN, one of the pull-down transistors M1 and M4 switches on to ground the corresponding one of the true and complement output nodes. Due to the feedback through the cross-coupled inverters 115 and 120, the non-grounded one of the true and complement output nodes is then charged to the I/O power supply voltage. The true input signal IN is thus level-shifted from the core power supply voltage to the I/O power supply voltage.
There are drawbacks to conventional level shifter designs. Conventional level shifters may output either a binary 0 or 1 when the input power domain collapses (e.g., at start-up, power failure, sleep or hibernation mode, or some other power transition). This output logic uncertainty may lead to unwanted leakage. Thus, in order to ensure a known state at power-up, costly asymmetrical designs are utilized. With reference to FIG. 1, note that the pull-down transistors M1 and M4 may be relatively large so that they can change the state of the latch formed by cross-coupled inverters 115 and 120. For example, if the state of this latch was such that the true output node was charged to the I/O power supply voltage, the PMOS transistor P1 was switched on. To flip the state of the latch such that the complement output node is instead charged to the I/O power supply voltage employs the pull-down transistor M1 to discharge the complement output node despite the PMOS transistor P1 initially being on and continuing to charge this node. A similar struggle occurs between pull-down transistor M4 and PMOS transistor P2 when flipping the latch from storing a logical one to storing a logical zero (the complement output node transitioning from charged to the I/O power supply voltage to being discharged). Making the pull-down transistors M1 and M4 relatively large compared to either of the inverter transistors M2 and M3 (and thus in turn to either of the inverter transistors P1 and P2) allows the struggle to be completed relatively quickly so that level-shifter 100 may have high-speed operation.
A similar difference in transistor size may ensure that level-shifter 100 has a known state at power-up. In particular, at power-up both the true input signal IN and its complement INB will be grounded such that both pull-down transistors M1 and M4 are off. The true output node and the complement output nodes for level-shifter 100 will also be grounded such that the inverter transistors M2 and M3 are also off. As the I/O power supply rises, both inverter transistors P1 and P2 will thus be initially on such that they charge their drains to cause the true output node and the complement output node to rise in voltage. Without any asymmetry for inverters 115 and 120, it may then be unpredictable which inverter transistor M2 and M3 would react more strongly to the charging of the true and complement output nodes by switching on. Such a random state for level-shifter 100 at power-up may be undesirable and can lead to glitches or other errors.
Thus, to ensure a known state at power-up, asymmetry is used in which one of the inverter transistors is made larger than the other. For example, inverter transistor M3 may be made several times larger than inverter transistor M2. Inverter transistor M3 will thus react to the charging of the complement output node at power-up by switching on more strongly than inverter transistor M2. Inverter transistor M3 will thus discharge the complement output node. This discharge reinforces the charging of the true output node such that level-shifter 100 will reliably output a binary zero (via an inverter—not shown) at power-up. Moreover, to further reinforce this known state, transistor P1 may be larger than transistor P2.
Although this asymmetry for the pull-down transistors and the latch provides a known start-up condition and enables high speed operation, asymmetric level shifters are relatively large and lower the density of level-shifter 100. Since level-shifters are used extensively, such large asymmetric designs occupy a large silicon wafer area which increases production costs. Accordingly, there is a need in the art for level-shifter arrays having a known start-up state and high-speed operation with improved density.